pb 1. Field of the Invention
The present invention relates to a method of making integrated circuits from wafers having improved flatness.
2. Description of the Prior Art
Integrated circuits are fabricated from semiconductor wafers according to various techniques known in the art. However, one universal operation is one or more lithography steps that define circuit features on the wafer. In a typical lithographic operation, optical radiation is projected through a "mask" that contains the desired features onto a resist coated surface of the wafer. It is imperative that the feature be defined with minimum distortion, which can be caused by various optical aberrations, including an out-of-focus condition. At the current state of the art, silicon semiconductor wafers are about 125 to 150 millimeters (5 to 6 inches) in diameter, and gallium arsenide wafers are perhaps 50 to 100 millimeters (2 to 4 inches) in diameter. In contrast, the features to be optically reproduced on each integrated circuit typically have dimensions as small as 1 micrometer or less. The limiting factors in the ability to reproduce such small features uniformly over all sites on a relatively large wafer include the flatness and parallelism of the wafer surfaces. These are limitations because the lithographic equipment necessarily has a depth of focus that is on the order of the smallest lithographic feature. Even automatic refocusing, often used for lithographic "steppers" that produce multiple images on the sites across the surface of the wafer, does not compensate for variations within a given exposure field. Therefore, specifications for wafer flatness and parallelism are becoming increasingly more stringent, and typically require a back side referenced site flatness of 0.6 micrometers or less, for example.
However, the ability to produce flat wafers is limited by the various shaping and surface refining operations required to produce the wafers. That is, in a typical sequence of operations for a silicon wafer, the wafer is first cut, as with a diamond saw, from a cylindrical ingot that may be grown by techniques known in the art. The wafer is then typically lapped in a Al.sub.2 O.sub.3 slurry to remove saw damage and obtain flatness. It is then etched in a solution of potassium hydroxide (KOH) to remove surface damage and debris caused by the lapping operation. At this point, both the front and back surfaces of the wafer are relatively flat, but have gouges and pits caused by the lapping and etching operations. That is, the lapping operation tends to form microscopic gouges in the surface, which are deepened and widened by the etching operation. The front side of the wafer is then polished, in order to remove the pits. The polishing is typically accomplished by mounting the wafer on a backing pad and rubbing the front surface against a soft polymer pad while flowing a colloidal silica slurry thereon. However, this polishing operation actually reduces surface flatness, mainly due to slight pressure variations across the wafer, and variations in the flow of the silica slurry. Hence, the front (i.e, polished) surface of the wafer becomes slightly uneven in terms of flatness and parallelism. It is therefore desirable to obtain wafers of the required smoothness and improved flatness and parallelism.